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Altera_Forum
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10 years ago

Problem with dynamic PLL reconfiguration

I am working on a project which involves dynamically configuring PLL to different frequencies. I have written a VHDL code for my requirement, however I am facing some circumstances in simulation w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

What does resetn_sig refer to in your design? Seems like this signal is not valid in the simulation.