Problem with Data Integrity & Clock between 2 FPGAs

If design has one fpga outputting to a DAC(for example) then you get DAC tSU/tH and enter constraints for FPGA outputs accordingly.

in your case you have two FPGAs. Now you have set input delays for FPGA2 on an arbitrary basis and got above tables for arrival times(the worst values to be taken as tSU/tH of FPGA2).

Now go to FPGA1 and set output delays based on FPGA2 figures for tSU/tH i.e. max output delay of tSU and min output delay as -tH

but if clk and data were in same direction(source synchronous).

In your case clk is opposite data and there is additionally pll phase shift so you need to work that out