Problem with Data Integrity & Clock between 2 FPGAs

normally, in case fpga outputs to a an ASIC (such as DAC) you will find out tSU/tH of DAC device and include board delays to set output delay constraints.

In your case fpga feeds fpga and so timing responsibility can be shared as both are configurable at io.

thus max output offset of fpga1 + tSU at fpga2 can equal clock period

However in practice you can first set input delays of fpga2 at some convenient values and see report(datasheet) to find out tSU/tH achieved at input pins. Then go to fpga1 and set output delays accordingly taking board delays into account