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However for understanding the problem, another question raised in my mind:
You said I should enter
reasonable constraints for IO delay constraint. What do you mean by reasonable here?
In my example, assume I want to use clk1 (no phase shift) to feed FPGA-1. How should I set my first trial of IO constraint? More specifically, what are
reasonable t_co_min, t_co_max, t_su & t_h values in the SDC file? What are the
starting point values?
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You need to learn how to use TimeQuest. The TimeQuest GUI shows you the timing waveforms for your given set of constraints, including by how much you fail. So you could start off with 0ns constraints and see by how much you fail. However, after you've done that once for an FPGA family, you'll know what "reasonable" means, so from that point on, you use reasonable constraints. Take a look at the figures in this document - they show screen captures from TimeQuest
https://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.pdf https://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.zip Cheers,
Dave
Honored Contributor
