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Altera_Forum
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11 years ago

Problem with Data Integrity & Clock between 2 FPGAs

Hi I have a problem with data integriry & clock between 2 FPGAs. A scheme of my design is inserted at the end. My design consists of 2 Cyclone III FPGAs. Each FPGA has several clock domains, eac...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks again.

First, my problem was resolved using IO constraints based on your SDRAM Nano Board template; Thanks.

Probably because my clock was not too high, I got answered though my IO constraints were set without an exact understanding of the problem. Nevertheless your guidelines helped me get out of the trouble.

However for understanding the problem, another question raised in my mind:

You said I should enter reasonable constraints for IO delay constraint. What do you mean by reasonable here?

In my example, assume I want to use clk1 (no phase shift) to feed FPGA-1. How should I set my first trial of IO constraint? More specifically, what are reasonable t_co_min, t_co_max, t_su & t_h values in the SDC file? What are the starting point values?