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I applied input_delay & output_delay constraints, thanks to your SDC guidelines.
In Cyclone III spreadsheets, t_su is negative. I inserted its value as a positive value.
t_h is copied from spreadsheet.
t_co is calculated according to Method-2 of AN-366.
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No, you've misunderstood the procedure. FPGA I/O cells have programmable delay elements, so there is no data sheet values for tsu/th/tco. The data sheets have "micro" parameters uTsu/uTh/uTco. Rather than try to calculate the delays by hand, you enter reasonable constraints, as I have above, and let Quartus/TimeQuest try to meet those constraints. For example, if the tco constraint above was too small, then TimeQuest would fail to meet that requirement. In that case, you would enter a slightly larger value (based on the failed result) and iterate. The above values were determined from a Stratix II FPGA design.
If you have to increase the tco from both Cyclone IIIs to meet the output timing, then you would edit the SDCs for both projects. The TimeQuest analysis of the inputs would then change, reflecting the increase in the delay on the other FPGA output. If you re-synthesize the design, then the programmable input delays will be adjusted, centering the setup/hold margin.
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After synthesis & programming FPGAs, still I have problem with data corruption.
What could cause problem?
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Poor PCB layout. Did you look at the clock waveform using an oscilloscope?
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Is sending out clock from a normal IO pin a good design practice?
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No, in general you should try to use a dedicated PLL output pin. Quartus will warn you that your use of a general I/O will result in excessive jitter. At 50MHz you should be fine though.
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One more question: Isn't it better that I feed FPGA-1 with clk1, instead of clk2? i.e. without 180 degree phase shift? is this phase shift in compliance with our constraints?
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TimeQuest analysis will answer this. Try with a common clock, and if timing cannot be met, see if the phase of the clock needs to be adjusted to meet timing. If that is the case, then use a PLL to adjust the phase. The SDRAM design I referred to has an example of this.
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What about output currents? is there a guideline to set output current? specially for clocks?
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It depends on your board design. Look at the clock waveform with a scope and try a few different settings to see if the signal integrity gets better or worse.
Cheers,
Dave
Honored Contributor
