Problem with Data Integrity & Clock between 2 FPGAs

I applied input_delay & output_delay constraints, thanks to your SDC guidelines.

In Cyclone III spreadsheets, t_su is negative. I inserted its value as a positive value.

t_h is copied from spreadsheet.

t_co is calculated according to Method-2 of AN-366.

After synthesis & programming FPGAs, still I have problem with data corruption.

What could cause problem?

Is sending out clock from a normal IO pin a good design practice?

One more question: Isn't it better that I feed FPGA-1 with clk1, instead of clk2? i.e. without 180 degree phase shift? is this phase shift in compliance with our constraints?

What about output currents? is there a guideline to set output current? specially for clocks?

Thanks