Problem with Data Integrity & Clock between 2 FPGAs

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Did I illustrate my point?

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Yes. However, you should never "assume" anything. The tool *can* analyze the interface timing, so you *should*.

My recommendation is to write an SDC file that includes the FPGA I/O timing requirements. Here's an outline for you ...

#  Timing parameters
set data_tsu     1.0
set data_th      1.0
set data_tco_min 0.0
set data_tco_max 6.0
#  Timing constraints
set data_input_delay_min    $data_tco_min
set data_input_delay_max    $data_tco_max
set data_output_delay_min  -$data_th
set data_output_delay_max   $data_tsu
#  Bidirectional buses
set data_io 
}]
#  Inputs
set data_i 
}]
#  Outputs
set data_o 
}]
#  Bidirectional buses
set_output_delay 
    -clock vclk_50MHz 
    -min $data_output_delay_min 
    $data_io
set_output_delay 
    -clock vclk_50MHz 
    -max $data_output_delay_max 
    $data_io
set_input_delay 
    -clock vclk_50MHz 
    -min $data_input_delay_min 
    $data_io
set_input_delay 
    -clock vclk_50MHz 
    -max $data_input_delay_max 
    $data_io
#  Inputs
set_input_delay 
    -clock vclk_50MHz 
    -min $data_input_delay_min 
    $data_i
set_input_delay 
    -clock vclk_50MHz 
    -max $data_input_delay_max 
    $data_i
#  Outputs
set_output_delay 
    -clock vclk_50MHz 
    -min $data_output_delay_min 
    $data_o
set_output_delay 
    -clock vclk_50MHz 
    -max $data_output_delay_max 
    $data_o

You'll need to edit this to define data_i, data_o, and data_io correctly. You'll also need to define your clocks correctly, eg., the output clock you generated. Take a look at this DE0-nano SDRAM example

http://www.alteraforum.com/forum/showthread.php?t=45927

There's an SDC file in that project that defines the SDRAM clock, and SDRAM I/O timing parameters. Since an FPGA data sheet does not really have a fixed set of timing parameters, use the ones I've given you above to start with, and then iterate as needed.

The other thing you can do is to look at the signals with a scope.

NOTE: You will need two different SDC files, one for each FPGA project.

Cheers,

Dave