problem with clocked video input and clocked video output

hi all:

I am using SOPC builder to process video ,my problem flow is

PAL video(720x576)--->ADV7189--->clocked video input --->clocked video output --->ADV7123.i use fpga os statix iii , now i get the fifo overflows .my problem is as follows:

1.how many pixes should i set the fifo of clocked video input and clocked video output so that it does not overflow?

2.the video input clock is 27MHZ and the SOPC clock is 100MHZ,is it ok?

if anyone can help me ,thank you very much!