Problem With Basically Everything

You forgot to list all the "_xuser" optional signals in the AXI spec :)

But honestly, most of them are not needed for most applications. Where most FPGA engineers would use AXI would be some external memory controller, and here you probably dont care about caching, quality of service, lock, protect and maybe not even ID. These are usally just left as a constants. Then the rest of the design will probably be AXI Streaming (which can connect pretty easily to the wdata/rdata channel). At least with AXI4 (over AXI3) you dont need to care about out of order write transactions. But a lot of these signals, while they do have meaning,

My only experience with non-zero readyLatency was in the Altera RapidIO core, where readyLatency is 1, and I had to connected it to an AXIS interface. Its not all that hard, you can just use a FIFO and connect ready to the almost full from the FIFO, and set the almost full threadhold to be "readyLatency". But it does mean a FIFO at every interface! Otherwise not much direct involvement with Avalon - just plumbing busses together in QSYS/SOPC.

Altera SoCs are dead. They missed the boat by a couple of years and Xilinx ran away with the Zynq parts (although they had had Hard PowerPC parts for years prior to these). So Altera didnt get any SoC traction and basically just abandoned them. Now they're trying to bring the x86/FPGA hybrid parts to market. Im in Xilinx land now so dont really know how its all coming along. But from the forum it seems most problems are coming from OpenCL users (which is what they're aiming the new parts at).