Problem With Basically Everything

Tricky,

Some good points. And if someone is just using a wizard to connect IP that understands AXI, the complexity does not matter. And to be fair, the Xilinx multiplier and other cores are using AXI stream which is quite simple. It sounds like you are referring to AXI Lite which is not too bad. My comments were based on my experience of having to implement a full AXI bus in my own user IP. Just listing the signals is exhausting and it requires a state machine to handle transactions:

    output  S_AXI_HP0_araddr,
    output   S_AXI_HP0_arburst,
    output   S_AXI_HP0_arcache,
    output   S_AXI_HP0_arid,
    output   S_AXI_HP0_arlen,
    output   S_AXI_HP0_arlock,
    output   S_AXI_HP0_arprot,
    output   S_AXI_HP0_arqos,
    input         S_AXI_HP0_arready,
    output   S_AXI_HP0_arsize,
    output        S_AXI_HP0_arvalid,
    output  S_AXI_HP0_awaddr,
    output   S_AXI_HP0_awburst,
    output   S_AXI_HP0_awcache,
    output   S_AXI_HP0_awid,
    output   S_AXI_HP0_awlen,
    output   S_AXI_HP0_awlock,
    output   S_AXI_HP0_awprot,
    output   S_AXI_HP0_awqos,
    input         S_AXI_HP0_awready,
    output   S_AXI_HP0_awsize,
    output        S_AXI_HP0_awvalid,
    input    S_AXI_HP0_bid,
    output        S_AXI_HP0_bready,
    input    S_AXI_HP0_bresp,
    input         S_AXI_HP0_bvalid,
    input   S_AXI_HP0_rdata,
    input    S_AXI_HP0_rid,
    input         S_AXI_HP0_rlast,
    output        S_AXI_HP0_rready,
    input    S_AXI_HP0_rresp,
    input         S_AXI_HP0_rvalid,
    output  S_AXI_HP0_wdata,
    output   S_AXI_HP0_wid,
    output        S_AXI_HP0_wlast,
    input         S_AXI_HP0_wready,
    output   S_AXI_HP0_wstrb,
    output        S_AXI_HP0_wvalid

I had to read the AXI spec in great detail and did not find it at all simple although the state machine did not end up being too complicated.

I've never had to deal with an Avalon bus where I didn't just respond in one clock cycle. I see in the Avalon spec that the default values for "ReadyLatency"/"waitrequestAllowance" you mention are 0 and the defaults for the others correspond with what I've called "simple". I see what you're saying; if those were nonzero, it would get VERY complicated! I agree, I'd rather deal with the 30 extra lines of AXI at that point. Can you point me to a core where that is the case (I'm just curious)?

We've used Lattice and Microsemi tools. Lattice is not too bad. Microsemi is bad and painfully slow and their chips are FLASH based so it takes several minutes to program them each time. Their PolarFire FPGA is actually impressive and makes Cyclone V look pretty dated, but we stayed with Altera due to tools and price. Neither has any real support and are nowhere near as good as Altera. To me, one of the best things about Altera was the superb free online training videos/labs for Quartus. They don't seem to be updating them for new releases though. And the Altera SoC training is pretty bad/nonexistant. If they are going to have a horrid SoC tool flow they could at least have good training for it. The NIOS tools are actually pretty reasonable; why in the world didn't they just replicate it?

My biggest concern at the moment is that all Intel seems to care about are high-end chips for servers and AI and those of us in the middle will be forgotten.