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You mention standard interfaces. Be careful what you wish for. Xilinx standardized on AXI for EVERYTHING! Even a multiplier. And worse, their SoC has AXI 3 but they decided to standardize cores on AXI 4 so you need bridges. AXI is a ridiculously complicated bus that serves no useful purpose for most FPGA cores. Thank you Altera for using a simple Avalon bus when possible.
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I would argue the other way around. AXI is very simple with no configuration paramters, Wheres Avalon has fewer connecting signals but loads of behavior parameters. All AXI channels behave the same - if ready and valid are high at the same time, a transaction occurs. This is NOT true of avalon, as you have that annoying "ReadyLatency"/"waitrequestAllowance" parameter meaning that if ready is de-asserted, you need to know how many cycles you have already been valid with ready low before you can stop sending. This makes debugging harder.
I can understand why Altera went this way, as years ago timing wasnt as good and so pipelining these things was a good idea. But now timing for logic cells is much easier, I prefer to see instantly whether a transaction occured or not.
There is also the argument the only people that use Avalon are Altera. When Altera had the Arm SoC parts the soc there was also AXI3, so is no blameless in this respect either. Then you had to bridge everything from AXI3 to Avalon also rubbish.
AXI is industry standard, many IP cores use AXI and so it can all talk to each other. If you try and port some 3rd party IP to Altera you'll probably need an Avalon AXI bridge. Add to that the free verification IP you can get for AXI, plus the other tons of vendor support it just makes your life easier. The Avalon verification IP is just rubbish (or non-existant). Altera are now stuck with Avalon as the majority of their IP uses it. And now they are Intel, even less incentive to use AXI.
In general though, Of all the people I know that have used both Altera and Xilinx tools, Altera is always the winner (I dont know anyone that has used lattice, MicroSemi or Atmel)
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