Problem With Basically Everything

I think we all feel your pain :), but the short answer to your question as to how Altera can have any market share is that Xilinx has their own set of issues.

I agree with most of your items, but if I can get around something reasonably easily I call it a nuisance. It is bizarre that Altera can't size and position dialogs and they often go off screen. Probably due to the use of some wizard to create the dialog and it only works on one screen resolution. But it's no more bizarre than Xilinx choosing a minute font for Vivado and declaring it to be a non-issue. I posted this 5 years ago and they still have not fixed it and there is no way around it:

https://forums.xilinx.com/t5/design-entry/how-do-i-increase-the-font-size-in-the-vivado-ide/m-p/349879/highlight/true#m15213

For the most part, I greatly prefer Quartus to Vivado. For example, I used to use Xilinx ChipScope. What a piece of garbage. SignalTap is a superb tool I use all the time. The thing that first motivated me to look at Altera was the Xilinx JESD204b core. I spent weeks (including a call to the developer in Scotland) to no avail. I tried Altera's JESD204b core and had it working in a few hours.

To me, Altera's number one downside is their ridiculous unusable SoC tool flow. The Altera SoC tool flow is so moronic, I may be forced back to Xilinx. I hate to do that because the Altera hardware is superior (another reason they have market share). Also, although the Xilinx SoC tool flow makes Altera looks foolish, the actual quality of the tools is not so good. For example, Xilinx has a long standing bug in their cache functions:

https://forums.xilinx.com/t5/embedded-development-tools/bug-s-in-xil-dcacheinvalidaterange-in-standalone-v-3-11-a/m-p/389395/highlight/true#m29482

Altera does not need such functions since they had sense enough to make peripherals cache coherent. I occasionally look at the Xilinx forums and laugh when I see posts to the effect of "... why are the last few bytes of my packet corrupt ...". I could go on and on about bugs in Xilinx SoC libraries. Just one more example:

https://forums.xilinx.com/t5/embedded-development-tools/driver-macros-need-parenthesis-around-arguments/m-p/365771/highlight/true#m28688

The Xilinx geniuses were not bright enough to put parenthesis in C macros. This is C programming 101. Instead of fixing the problem, throughout the Xilinx drivers you would see things like XEmacPs_Transmit((&emac)); where they put the () at the call instead of in the macro.

You mention standard interfaces. Be careful what you wish for. Xilinx standardized on AXI for EVERYTHING! Even a multiplier. And worse, their SoC has AXI 3 but they decided to standardize cores on AXI 4 so you need bridges. AXI is a ridiculously complicated bus that serves no useful purpose for most FPGA cores. Thank you Altera for using a simple Avalon bus when possible.

These are just examples to show that both have issues. To me, Altera's issues are much more easily fixed but they don't seem to have any intention of doing so. Developers tend to want to work on "fun" stuff and Altera management needs to say you can't do that until some fundamental tool issues are fixed.

The number two Altera downside would have to be Qsys but this could go on forever. I avoid it to the extent possible, but you can't when using the SoC tools.

I guess I would change your post to ask "How to either one of these companies have any market share :) ?"