problem with a multiprocessor system

What about timing reports? I've tried to use Nios + some additional DMA controllers, written by myself, sharing the same SDRAM chip. I wasn't able to run Nios + more than 4 DMA cores on the same chip. That was Nios + 2 writing to memory DMAs and 2 reading from memory DMAs. Timing report showed, that the interconnect is not able to switch between masters fast enough. My target is Nios + 14 DMA cores (total of 7 streaming channels), so I had to redesign the PCB to use at least on chip per two channels: 1 chip -> 4 DMAs. So 7 channels has 4 chips and Nios has separate SDRAM chip.