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Honored Contributor
Honored ContributorProblem Vhdl the process with Reset option
I have written VHDL code for VGA controller for spartan 3E board. The code simulates and works well without the reset and clk process in the code below. But after inserting the process(reset,clk) the...
Altera_ForumHonored Contributor
Honored ContributorHJS noticed one of big VHDL coding errors.
by the way of shivukumar's code, there will be conflicts that the simulator solves with resolving functions in std_logic packages. It is like connecting 2 outputs together ! I may add : Use STD_uLOGIC and STD_uLOGIC_VECTOR.
