Altera_Forum
Honored Contributor
Honored Contributorproblem sdram controller read/write FIFOs. NEED HELP !
hello all
Please i need your help , i've been strugling with this problem for a while. well i would like to display two images on a vga screen. and i'm using the sdram to temporarely save frames before display. when i was using only one image i didn't have any problem i had two write fifo and two read fifo. but when i attempt to write/read another image means i added two other FiFOs for the write and two other read Fifos for the read, i get a mess on the vga display, knowing that i added a display module to select to decide where to display the image since i divided the screen into 2. if (WR1_LOAD)
rWR1_ADDR <= WR1_ADDR;
else
if (mWR_DONE&&WR_MASK)
begin
if (rWR1_ADDR<WR1_MAX_ADDR-WR1_LENGTH)
rWR1_ADDR <= rWR1_ADDR+WR1_LENGTH;
else
rWR1_ADDR <= WR1_ADDR;
end
// Write Side 2
if (WR2_LOAD)
rWR2_ADDR <= WR2_ADDR;
else if (mWR_DONE&&WR_MASK)
begin
if (rWR2_ADDR<WR2_MAX_ADDR-WR2_LENGTH)
rWR2_ADDR <= rWR2_ADDR+WR2_LENGTH;
else
rWR2_ADDR <= WR2_ADDR;
end
// Write Side 3
if (WR3_LOAD)
rWR3_ADDR <= WR3_ADDR;
else
if (mWR_DONE&&WR_MASK)
begin
if (rWR3_ADDR<WR3_MAX_ADDR-WR3_LENGTH)
rWR3_ADDR <= rWR3_ADDR+WR3_LENGTH;
else
rWR3_ADDR <= WR3_ADDR;
end
// Write Side 4
if (WR4_LOAD)
rWR4_ADDR <= WR4_ADDR;
else if (mWR_DONE&&WR_MASK)
begin
if (rWR4_ADDR<WR4_MAX_ADDR-WR4_LENGTH)
rWR4_ADDR <= rWR4_ADDR+WR4_LENGTH;
else
rWR4_ADDR <= WR4_ADDR;
end
// Read Side 1
if (RD1_LOAD)
rRD1_ADDR <= RD1_ADDR;
else if (mRD_DONE&&RD_MASK)
begin
if (rRD1_ADDR<RD1_MAX_ADDR-RD1_LENGTH)
rRD1_ADDR <= rRD1_ADDR+RD1_LENGTH;
else
rRD1_ADDR <= RD1_ADDR;
end
// Read Side 2
if (mRD_DONE&&RD_MASK)
begin
if (rRD2_ADDR<RD2_MAX_ADDR-RD2_LENGTH)
rRD2_ADDR <= rRD2_ADDR+RD2_LENGTH;
else
rRD2_ADDR <= RD2_ADDR;
end
// Read Side 3
if (RD3_LOAD)
rRD3_ADDR <= RD3_ADDR;
else if (mRD_DONE&&RD_MASK)
begin
if (rRD3_ADDR<RD3_MAX_ADDR-RD3_LENGTH)
rRD3_ADDR <= rRD3_ADDR+RD3_LENGTH;
else
rRD3_ADDR <= RD3_ADDR;
end
// Read Side 4
if (mRD_DONE&&RD_MASK)
begin
if (rRD4_ADDR<RD4_MAX_ADDR-RD4_LENGTH)
rRD4_ADDR <= rRD4_ADDR+RD4_LENGTH;
else
rRD4_ADDR <= RD4_ADDR;
end
end
Sdram_Control u7 ( // HOST Side
.RESET_N(KEY),
.CLK(sdram_ctrl_clk),
// // FIFO Write Side 1
.WR1_DATA({1'b0,sCCD_G,sCCD_B}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*480/2),
.WR1_LENGTH(8'h50),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(PIXCLK),
//
// // FIFO Write Side 2
.WR2_DATA({1'b0,sCCD_G,sCCD_R}),
.WR2(sCCD_DVAL),
.WR2_ADDR(23'h25800),
.WR2_MAX_ADDR(23'h25800+640*480/2),
.WR2_LENGTH(8'h50),
.WR2_LOAD(!DLY_RST_0),
.WR2_CLK(PIXCLK),
//
// // FIFO Write Side 3
.WR3_DATA(data_test1),
.WR3(valid),
.WR3_ADDR(23'h60000),
.WR3_MAX_ADDR(23'h85800),
.WR3_LENGTH(8'h50),
.WR3_LOAD(!DLY_RST_0),
.WR3_CLK(PIXCLK),
//
// // FIFO Write Side 3
.WR4_DATA(data_test2),
.WR4(valid),
.WR4_ADDR(23'h90000),
.WR4_MAX_ADDR(23'h90000+640*480/2),
.WR4_LENGTH(8'h50),
.WR4_LOAD(!DLY_RST_0),
.WR4_CLK(PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(vga_read),
.RD1_ADDR(0),
.RD1_MAX_ADDR(640*480/2),
.RD1_LENGTH(8'h50),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(~VGA_CTRL_CLK),
//
// // FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(vga_read),
.RD2_ADDR(23'h25800),
.RD2_MAX_ADDR(23'h25800+640*480/2),
.RD2_LENGTH(8'h50),
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(~VGA_CTRL_CLK),
////
////// // FIFO Read Side 1
.RD3_DATA(Read_DATA3),
.RD3(vga_read),
.RD3_ADDR(23'h60000),
.RD3_MAX_ADDR(23'h85800),
.RD3_LENGTH(8'h50),
.RD3_LOAD(!DLY_RST_0),
.RD3_CLK(~VGA_CTRL_CLK),
////
// // FIFO Read Side 2
.RD4_DATA(Read_DATA4),
.RD4(vga_read),
.RD4_ADDR(23'h90000),
.RD4_MAX_ADDR(23'h90000+640*480/2),
.RD4_LENGTH(8'h50),
.RD4_LOAD(!DLY_RST_0),
.RD4_CLK(~VGA_CTRL_CLK),
// SDRAM Side
.SA(DRAM_ADDR),
.BA(DRAM_BA),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM(DRAM_DQM)
);
