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Hi,
i have used EP2C5F256I8 in my project,which requires 16 mhz clk to be converted into 32 mhz clk and i have generated a pll using megawizard.I would like to know whether
- the output of the pll must be locked.
- and i have seven modules that is to be driven by pll clk, can it be connected by signal from instantiated pll block.
Kindly help me by providing some information. Thank You.
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Hi,
if you would like to check whether the pll is locked or not, you can define a lock signal
with the megawizard. When you assign the signal to an FPGA pin your can check it
easy with a scope. You can connect all your modules to the pll output.
Kind regards
GPK
Honored Contributor
