problem interfacing DDR2 Memory Device with stratixIII

Hi all

in now days i need to design long FIFO Using DDR2 Memory device.

I Build a controller to the Memory Using QSYS.

I designed interface to the AVALON Bus in verilog.

for the first debug i create ROM with known data pattern and feed it to the ddr2 using my interface.

In the SIGNAL TAP i see the AVALON BUS signal as well as described in the Avalon Spec but when i write i didn't get the waitrequest signal asserted by the controller.

The waitrequest is probably my acknowledge that the ddr2 write my data.

Does somebody can help me to solve this issue ? - i checked all the IO assignment and location and it looks good ( i using stratixIII development board).

How can i debug the ddr2 in other way?

Itamar