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Altera_Forum's avatar
Altera_Forum
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8 years ago

Problem in Inter FPGA Transfer

hi, I am having a customized board with 2 Stratix V FPGA on it. i wanted to transfer the data from one FPGA to another directly ( Pin to Pin ) without ant protocol. The clock rate is 10 Mhz . ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

If you just send data + clock, you can just invert the clock on the reception part to sample the data in the eye of the signal.

The input_delay / output_delay commands will probably be useless at 10MHz.