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hi,
I am having a customized board with 2 Stratix V FPGA on it. i wanted to transfer the data from one FPGA to another directly ( Pin to Pin ) without ant protocol. The clock rate is 10 Mhz .
I am finding that the data received is not same as what i had sent. The problem is in the SDC file in which i had given the INPUT_DELAY and OUTPUT_DELAY commands.
Kindly suggest me how to find the accurate delays to be given in SDC file and what other commands i should enter to get the correct data .
Saurabh
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You need to describe the protocol you are using in more detail. Is it a single data line, as in a serial UART but at 10MHz baud rate? Or is it embedded clock/data as would be in NRZ/NRZI encoded? Or do you have a separate clock line and data line? Or ... ?
It sounds like you have more than one signal (like clock + data), as the data input/output delay on a single line would not be an issue.
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