Probelm with DM9000A control

Hi,

what should I do to drive ethernet DM9000A? I have VHDL code, which I rewrite from original Verilog DM9000A_IF in DE2-70 Ethernet demo.

entity DM9000A_IF is
	generic(
		W_DATA : positive := 16
	);
	port(
		-- HOST Side
		-- Signals fro Avalon-MM slave port "s1"
		avs_s1_writedata_iDATA : in std_logic_vector(W_DATA - 1 downto 0);
		avs_s1_readdata_oDATA : out std_logic_vector(W_DATA - 1 downto 0);
		avs_s1_address_iCMD : in std_logic;
		avs_s1_read_iRD : in std_logic;
		avs_s1_write_iWR : in std_logic;
		avs_s1_chipselect_n_iCS_N : in std_logic;
		avs_s1_reset_n_iRST_N : in std_logic;
		avs_s1_clk_iCLK : in std_logic; -- 50MHz
		avs_s1_irq_oINT : out std_logic;
		-- Export signal to DM9000A Chip
		avs_s1_export_ENET_DATA : inout std_logic_vector(W_DATA - 1 downto 0);
		avs_s1_export_ENET_CMD : out std_logic;
		avs_s1_export_ENET_RD_N : out std_logic;
		avs_s1_export_ENET_WR_N : out std_logic;
		avs_s1_export_ENET_CS_N : out std_logic;
		avs_s1_export_ENET_RST_N : out std_logic;
		avs_s1_export_ENET_INT : in std_logic;
		avs_s1_export_ENET_CLK : out std_logic
	);
end DM9000A_IF;
architecture a_DM9000A_IF of DM9000A_IF is
	signal clk : std_logic;
begin
	avs_s1_export_ENET_DATA 	<=	avs_s1_writedata_iDATA when avs_s1_write_iWR = '1' else (others => 'Z');
	avs_s1_readdata_oDATA		<=	avs_s1_export_ENET_DATA when avs_s1_read_iRD = '1' else (others => 'Z');
	avs_s1_export_ENET_RST_N	<=	avs_s1_reset_n_iRST_N;
	avs_s1_irq_oINT			<=	avs_s1_export_ENET_INT;
	avs_s1_export_ENET_CMD		<=	avs_s1_address_iCMD;
	avs_s1_export_ENET_CS_N		<=	avs_s1_chipselect_n_iCS_N;
	avs_s1_export_ENET_RD_N		<=	not avs_s1_read_iRD;
	avs_s1_export_ENET_CLK		<=	clk; -- 25MHz
	avs_s1_export_ENET_WR_N <= not avs_s1_write_iWR;
	process (avs_s1_clk_iCLK, avs_s1_reset_n_iRST_N)     -- For 50MHz -> 25MHz
	begin
	
		if (avs_s1_reset_n_iRST_N = '0') then
			clk <= '0';
		
		elsif (rising_edge(avs_s1_clk_iCLK)) then
			clk <= not clk;
		
		end if;
		
	end process;
end a_DM9000A_IF;

In Quartus Pin Assignement I have these appropriate signals coresponding to datasheet.

ENET_DATA <- set as bidirectional

ENET_CMD

ENET_RD_N

ENET_WR_N

ENET_CS_N

ENET_RST_N

ENET_INT

ENET_CLK <- my 25MHz

I read from registers bad values instead of values which I wrote to it. Initialization in C is also from demo. No LEDs blink.

But when I try DE2-70 Ethernet demo it works.