preserve_hierarchy assignment

Hello ,

Do you prefer VHDL ? I am a VHDL user

And I prefer to use Attibute to keep the node in Logic Design

instead of setting the "preserve register" assignment in the Q II Assignment Editor

This applicable to all register nodes

There are two useful attributes which are "syn_preserve" and "syn_keep"

syn_preserve is used for keeping the register node , avoid being synthesized away

syn_keep is used for keeping the net , to my understanding (I am not sure if it's correct) , it keeps the node so that user can find the node in node finder , but it doesnt guarantee the logic is kept there.

Usually I focus on the register nodes and I do not care about those combinational nodes in the design

Here is an example :

In the signal declaration part :

signal Din_p0 : std_logic_vector(15 downto 0);

attribute syn_preserve : boolean;

attribute syn_preserve of din_p0 : signal is true;

Then the Din_p0 will be preserved

Another Example

signal Q0 : std_logic;

signal Q1 : std_logic;

begin

process (clk, A, B)

begin

if clk = '1' and clk 'event then

Q0 <= A and B;

Q1 <= A and B;

end if;

end process;

end behavioral;

Then Quartus will preserve DFF for node Q0 and node Q1

Hope it helps

Samson