Honored ContributorHI,
What will happen to IO pins voltage if the VCCIO supply is powered ON before VCCINT supply during initial board Power-UP? Take note that during initial power-UP the FPGA is in unknown state. Does it cause some voltage glitch of several milliseconds across I/O pins during initial power up? Regards,
Honored ContributorThis depends on what device family you're using, what the documentation states and whether that device will tolerate the power up sequence you're presenting it.
Most Cyclone families offer "Support for any power-up sequence". I/O pins will remain tri-stated until the device is happy all the required rails are present. This will include VCCINT & VCCIO for banks containing pins with configuration functions. So, given your description, pins would remain tri-state. Cheers, Alex
