--- Quote Start ---
But That isnt a "reset state", I dont have one. If I were to make a reset state, how would it know when to transition to my initial "wait_state"?& why do you need one?
--- Quote End ---
It might be OK for your wait_state to be the state the state machine enters at power-up reset. If that state waits for some signal that is synchronized to the clock before transitioning to any other state, then you're OK. If the end of the power-up reset condition could cause an immediate exit from that state, then you have to make sure only one state code bit can potentially toggle for that exit or you have to use a synchronized reset signal (whether from an input pin or created internally) to control the exit from that state.
--- Quote Start ---
It sounds you are saying "most designs" use an external power on reset to drive DEV_Clrn, but I am trying to get around that.
--- Quote End ---
Most designs have a reset on a regular input pin, not the DEV_CLRn special-purpose pin for device-wide reset. You can't use DEV_CLRn in your RTL for a reset signal.
Honored Contributor
