Power on Reset & state machines

In the other thread, I was trying to guess what Whitebird was trying to do. I referred you to my post in that thread just for the discussion of a state machine powering up with all state code bits low unless you override that with a reset signal.

All registers will power up low without a reset signal, and you can make your design safely use all registers low as the intended reset condition without using a reset signal. You can make your state machine have all bits low in the state code of the reset state and have only one state code bit toggle for the state transition to exit the reset state. Unless you want to be able to force the reset state later without cycling power, you don't have to use a reset signal.

Without a synchronized reset signal, though, registers might exit the reset condition at different clock cycles. In most designs an external reset signal is input to the CPLD and held asserted until power has been applied long enough for it to be OK to start operation of the CPLD's logic. A proper design also synchronizes the reset signal to the clock and uses recovery and removal analysis unless the designer is careful to ensure that it is actually OK for registers to exit reset at different clock cycles.

My suggestion in the other thread to create an internal reset signal (which does not use a device input pin) was just for the case where you do not always assert an external reset input at power up and you need to guarantee that more than one register comes out of reset on the same clock cycle. I suggested having a register that has its input hard tied to high, not driven by a high input pin. You might have to do some trick to keep synthesis from synthesizing away such a register.

A state machine in particular might require multiple registers to exit reset at the same clock cycle. If more than one bit in the state code changes for a valid transition from the reset state to another state, you have to be sure all those potentially changing bits see the reset end at the same clock cycle so that they all change together for a valid state transition.

If you are using Quartus integrated synthesis, then in the Quartus handbook see Volume 1, Section III, Chapter 8. Read the "State Machine Processing" section and the following sections. The handbook tells you how you can optionally encode your states manually (there's also a VHDL template in the text editor for this).

For automatic one-hot encoding (and I'm guessing for other encodings that are not user-specified), this section of the handbook says, "Quartus II integrated synthesis encodes the initial state with all zeros for the state machine power-up because all device registers power up to a low value." I didn't know whether "the initial state" means the first state listed in the type definition or if synthesis determines it from a reset signal in the state machine to make the power-up reset state match the one controlled by the reset signal. I did an experiment and found that the state forced by an asynchronous reset signal (I didn't try a synchronous reset signal) is always the one that gets encoded with all state bits low when "State Machine Processing" is set to "Auto". The all-bits-low state isn't necessarily the first one listed in the type definition.

Check the Analysis & Synthesis report for the actual state encoding. It is shown in messages and in a table.