Power on Reset & state machines

Brad, wow thanks, nice quick reply, really appreciate it! I think I understand what your saying , but let me make sure. So you would tie an input pin high, & read it & then when you read a high, you know you've entered user mode & everything should be cleared. Then you'd generate a reset signal based on this sample of a high.. so in the vhdl world, it would be something like this?:

the pin i tied high is input_pin

my generated reset is umm.. generated_reset :)

process(clk)

begin

if clk = '1' and clk'event

if input_pin = '1' and reset_done = '0' then

reset_done <= '1';

generated_reset <= '1';

elsif generated_reset = '1' then

generated_reset <= '0';

end if;

end if;

end process;

it should make a generated_reset signal 1 clk cycle wide after entering user_mode, that is of course, if i understand you correctly..

thanks again,

ambien