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Hello,
I want a 5400 Mbps receive with a 135 MHz reference clock to the CDR. In the same transceiver I want a 2970 Mbps transmit driven by a 1485 MHz clock generated in a fPLL. When I try to set this up in a native transceiver in Quartus 12.1 I get an error that the 5400 data rate is invalid because it doesn't work for the transmitter. This is true, but the transmitter will be working at 2970 Mbps driven by the fPLL clock.
Is it possible to use completely different rates for TX and RX in a single Arria V transceiver if the TX PLL is used for CDR and a fractional PLL is used as the transmit PLL?
Thanks,
Mark.
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Hi Mark,
I am facing today the same question: I'd like to implement a full-duplex transceiver with a 4096Mbps RX data rate and 5120Mbps TX data rate in an ArriaV GX.
My system reference clock is 128MHz (4096=32x 128MHz, 5120=40x 128MHz).
Playing a bit with the Arria V Transceiver native PHY Megafunction, I didn't see a place in the MegaWizard where I could specify different TX and RX data rates ("Standard PCS" enabled).
Therefore, I'm concluding it remains possible if I am instantiating a TX-Only + a RX-Only variations.
On your side, did you finally succeed in having different TX and RX data rates and how did you instantiate the transceiver megafunction ?
Thanks,
Olivier
Honored Contributor
