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Altera_Forum's avatar
Altera_Forum
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13 years ago

Possible reasons for "downloading .elf process failed/leaving targt process paused""

Good day to all,

  • This is the evergreen problem of every altera users and they must have faced at some point of time before.

  • Sometimes We wondered,"we didnot harrase our design that much and why suddenly this error".

  • Some would create again the whole system from the scatch,and solved ( as I did in past ;) ).

  • I just want from everyone what can be the very basic root causes for this problem ?

  • I have faced this problem before and as per as I know and the way I solved,I am listing out the very very basic causes.( i know other reasons might be there but i am saying about very basic reason that come up first into our mind )

By assuming,our hardware's are functioning properly ( i.e.memories ),

1. If our design doesnot meet timing requirements . ( dont know ? read Rysc timequest userguide,best one...! )

2. Clock and reset issues.

3. Problems in pin assignments.

Altera says,http://www.altera.com/support/kdb/solutions/spr343469.html (http://www.altera.com/support/kdb/solutions/spr343469.html)

Apart from this,if you know more and want to share your frustration and how you solved,please share your knowledge.This can help many people.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    if you use sdram in your project, mybe your vhdl code has some problems.

    i used "tut_DE2_sdram_vhdl" to create project and test sdram

    pay attention to inputs and outputs, some pins like DRAM_DQ is inout pin;

    and this code in "tut_DE2_sdram_vhdl" is incorrect

    BA <= (DRAM_BA_1 & DRAM_BA_0);

    DQM <= (DRAM_UDQM & DRAM_LDQM);

    and must be replaced by this codes.

    DRAM_BA_1 <= BA(1);

    DRAM_BA_0 <= BA(0);

    DRAM_UDQM <= DQM(1);

    DRAM_LDQM <= DQM(0);

    pay attention. DRAM_BA_1, DRAM_BA_0, DRAM_UDQM, DRAM_LDQM are output pins, so the code about sdram that is given in "tut_DE2_sdram_vhdl" dose not asign any signal to

    this pins, so when you running a program by nios II eclipse or altera monitor program or altera debug client you mybe see this errors:

    1-

    Downloading ELF Process failed!

    2-

    Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

    Resetting and pausing target processor: OK

    Initializing CPU cache (if present)

    OK

    Downloading 00800000 ( 0%)

    Downloading 00803804 (87%)

    Downloading 01001000 (99%)

    Downloaded 15KB in 0.2s (75.0KB/s)

    Verifying 00800000 ( 0%)

    Verify failed between address 0x800000 and 0x803107

    Leaving target processor paused

    by changing the tow line of code, that described above, the problem will be solved.

    pll settings and configuration must be done accordance to "tut_DE2_sdram_vhdl" document;

    DRAM_CLK assignment by pll is so important. for example this done in "tut_DE2_sdram_vhdl" document, by

    neg_3ns: sdram_pll PORT MAP (CLOCK_50, DRAM_CLK);

    if you create a project in Quartus, after changing and compiling the project you must regenerate the bsp in nois II Eclipse if you use this program to write c code for nios II processor.

    the problem solved:

    Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

    Resetting and pausing target processor: OK

    Initializing CPU cache (if present)

    OK

    Downloading 00800000 ( 0%)

    Downloading 00803B60 (88%)

    Downloading 01001000 (99%)

    Downloaded 15KB in 0.2s (75.0KB/s)

    Verifying 00800000 ( 0%)

    Verifying 00803B60 (88%)

    Verifying 01001000 (99%)

    Verified OK

    Starting processor at address 0x00800194

    i'm not good in English, so ...