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Altera_Forum
Honored Contributor
Honored ContributorPLL's in Cyclone V
Hello, I am trying to use the output of a PLL to drive a logic in FPGA. I'm not sure which clock should be connected as the 'refclk' for the PLL and how the 'outclk' of the PLL should clock my ...
Altera_ForumHonored Contributor
Honored ContributorHi,
Can you post larger image of the input clocks/ PLL signals and your outputs. Also put in your code in the editor window using "code" blocks so we can take a look at it. Maybe able to help you after we get a better picture of what you are trying to do here.
