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Honored Contributor
Honored ContributorPLL's in Cyclone V
Hello, I am trying to use the output of a PLL to drive a logic in FPGA. I'm not sure which clock should be connected as the 'refclk' for the PLL and how the 'outclk' of the PLL should clock my ...
Altera_ForumHonored Contributor
Honored ContributorHi,
Output will be not available when PLL is not locked. Check the PLL configuration. If the input clock remains within the minimum and maximum frequency specifications, the PLL is able to achieve lock. Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
