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Altera_Forum
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8 years ago

PLL's in Cyclone V

Hello, I am trying to use the output of a PLL to drive a logic in FPGA. I'm not sure which clock should be connected as the 'refclk' for the PLL and how the 'outclk' of the PLL should clock my ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hello eapenabrm,

I measured the outclk of the PLL using Signal Tap, looks like it is generating some signal. Although there is no output at the HSMC pin (PIN_B13), this is where I measure the signal for all the logic I have implemented till date (it worked fine up until I started using PLL's). I have attached some screenshots to provide a better perspective of the problem.

data_out is where I measure the output signal on the HSMC which has a daughter board connected to it.

Thank you very much for your help.