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Honored Contributor
Honored ContributorPLL's in Cyclone V
Hello, I am trying to use the output of a PLL to drive a logic in FPGA. I'm not sure which clock should be connected as the 'refclk' for the PLL and how the 'outclk' of the PLL should clock my ...
Altera_ForumHonored Contributor
Honored ContributorHi,
The clocks on your board are derived from the Si5338 Oscillator . The pins that are connected to the FPGA are : Y26, AF14, AA16, K14. These are the 50MHz clocks that are connected from the Si5338 to the FPGA. You could try any of these. These are the clock assignments from the QSF file for the board.. set_location_assignment PIN_Y26 -to clk_100m_fpga set_location_assignment PIN_K14 -to clk_50m_fpga set_location_assignment PIN_AA16 -to clk_top1 set_location_assignment PIN_AF14 -to clk_bot1 set_location_assignment PIN_AA26 -to hsmc_clkin_p[1] set_location_assignment PIN_H15 -to hsmc_clkin_p[2] set_location_assignment PIN_E7 -to hsmc_clkout_p[1] set_location_assignment PIN_A11 -to hsmc_clkout_p[2] set_location_assignment PIN_J14 -to hsmc_clk_in0 set_location_assignment PIN_AD29 -to hsmc_clk_out0 After making the pin assignments, you need to make sure that the PLL in your design is using the clock from the mentioned pins. Also check if there are any Jumpers/ settings for clock selection on the board.
