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Altera_Forum
Honored Contributor
Honored ContributorPLL's in Cyclone V
Hello, I am trying to use the output of a PLL to drive a logic in FPGA. I'm not sure which clock should be connected as the 'refclk' for the PLL and how the 'outclk' of the PLL should clock my ...
Altera_ForumHonored Contributor
Honored ContributorHi Anand,
I used the Signal Tap to monitor the refclk of PLL and looks like it is not being clocked. Seems strange as I connected the top level input clock port to the instantiated PLL (Altera-PLL). I think I am missing some information about dedicated clocks for PLL's. The board is Arrow SoCkit evaluation with Cyclone 5. Board Number: 5CSX5C6D631C6
