Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorPLL's in Cyclone V
Hello, I am trying to use the output of a PLL to drive a logic in FPGA. I'm not sure which clock should be connected as the 'refclk' for the PLL and how the 'outclk' of the PLL should clock my ...
Altera_ForumHonored Contributor
Honored ContributorHi,
Are you using development kit? Check/Monitor the clock 50Mhz refclk input Using signal-tap for the debug. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
