PLL warning about clkin pin location

Hi,

Yes, you have used dedicated clock input pin. As per the recommended pin assignments in the Quartus II software for the PLL input is

• inclk[1,0] – dedicated clock input pin (CLK[15..0]) & you have used clk9.

Which PLL have been used? (PLL1,PLL2,PLL3 or PLL4?)

Assuming PLL1, try by selecting clock from CLK[3..0] or CLK[15..12] {PINS=E2,E1,M2,M1,R8,T8,R9,T9}

Check if you are getting same Warning.

Other recommendation.

The PLL input clock must be either dedicated input clock pins or another PLL output. The PLL input clock cannot be driven from internal logic. The PLL output clock should be connected to its dedicated clock output pin for optimum routing (only applies to c0), user I/O, or global clock (GCLK).

If you want compensation of the specified input clock or better jitter performance,connect the input clock only to an input pin, or assign the input pin only to a dedicated input clock location for the PLL.

If you do not want compensation of the specified input clock, then set the PLL to No Compensation mode.

Regards

Anand