PLL usage

Hello all,

I've noticed that many use PLL on the reference clock input even if they do not need to divide/multiply/shift this clock or do not have external clock to synchronize to the reference frequency.

For example 50 MHz input clk goes to PLL and then 50MHz c0 is used everythere in the design.

What is the purpose of this type of PLL usage?

Thank you in advance.