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Altera_Forum
Honored Contributor
Honored ContributorPLL usage
Hello all, I've noticed that many use PLL on the reference clock input even if they do not need to divide/multiply/shift this clock or do not have external clock to synchronize to the reference fr...
Altera_ForumHonored Contributor
Honored ContributorYou cannot drive the PLL from internally generated logic. It can be driven from a global route through an input pin. It can also be driven from the output of another PLL.
The only way you might be able to fake it out is if you have a feedback path on the board so you can drive a clock out of the FPGA and into a suitable clock pin. What is it you're trying to accomplish by switching between the two clocks? Maybe there is another approach. Jake
