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Altera_Forum
Honored Contributor
Honored ContributorPLL usage
Hello all, I've noticed that many use PLL on the reference clock input even if they do not need to divide/multiply/shift this clock or do not have external clock to synchronize to the reference fr...
Altera_ForumHonored Contributor
Honored ContributorAs another note, the minimum closed-loop bandwidth for an enhanced PLL in Stratix II GX is 130kHz. So if you manage to configure your PLL with a bandwidth of 130kHz, you will filter out a great deal of jitter (at frequencies higher than 130kHz) from the input clock. However, doing so also makes the PLL more susceptible to jitter induced by noise from the PLL's VCO which includes noise on the PLL's power supply.
Jake
