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Altera_Forum
Honored Contributor
Honored ContributorPLL usage
Hello all, I've noticed that many use PLL on the reference clock input even if they do not need to divide/multiply/shift this clock or do not have external clock to synchronize to the reference fr...
Altera_ForumHonored Contributor
Honored ContributorClock uncertainty is as a time domain parameter in the Quartus vocabulary, jitter is actually a part of it.
I didn't take part in the previous discussion und don't want to bring it up again. But I don't read much jitter removing capability from the PLL specifications. Simplified, they say, if your input clock has a jitter, use a fast bandwidth setting to allow the PLL to follow it. Consequently, the timing analysis adds input clock jitter to the overall uncertainty.
