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Honored Contributor
Honored ContributorPLL Tuning
Hello. I am slightly confused about tuning a PLL output for an SDRAM clock and wondered if someone here could answer a couple of questions. Following this example [http://www.altera.co.k...
Altera_ForumHonored Contributor
Honored ContributorHi.
OK ive done the PLL tuning and my memory is working very well, thanks again! I was wondering if someone could check something for me however. As it is now, I can take the memory up to 90Mhz and it passes the simple tests fine, but if I take it to 100 it starts to fail. The reason I suspect it might be my calculations for the PLL tuning as opposed to simply limitations of my board is because 90Mhz is the frequency at which the Tclk period becomes small enough that the Lead & Lag times of the read operations become smaller than those of the write operations. The phase shift calculated at 90Mhz is almost identical for that calculated for all frequencies below it, but any higher and it deviates more and I begin to encounter errors. My SDRAM has the following parameters: Tac/hz = 5.4 Toh = 2.7 Tsu = 1.5 Th = 0.8 The timing analysis reports for my FPGA: Tsu (smallest for SDRAM pins) = -0.493 Tco (highest for SDRAM pins) = 7.008 Th (highest for SDRAM pins) = 0.679 I have calculated my phase shift as +1.8005ns at 100Mhz SDRAM clock. Does this look right?
