PLL Tuning

Hi Cris72.

Thanks, those equations are making more sense now.

So essentially what those equations are working out is the maximum amount of time the SDRAM clock can rise before the system clock (which all the SDRAM data are synchronized to), the first equation being for write and the second for read. So you take the minimum of these so no matter whether reading or writing its never too far out. Is that correct?

Then you calculate a similar value for the lag, and that provides the window around the system clock edge that the SDRAM clock can operate in, and you adjust the phase so that it sits in the centre of this, right?

As for the timing analysis (using Classic), I can see the reports for tsu, tco and th for the FPGA, but I had a couple of questions about using them:

1. I take it I should take the worst case values for the pins relating to the memory rather than the worst case for the entire design right?

2. In the lead/lag equations they use the maximum and minimum clock to output delay (tcout) of the FPGA, but my timing analysis report only has one set, which I am assuming are the maximum. Am I missing something or do we just use these?

Thanks again.