PLL Tuning

Hi sebastian,

- system clock is the clock which feeds to your internal fpga devices, i.e. Nios processor or other devices configured in fpga

- sdram clock is the clock signal which goes outside and drives the clk pin on the sdram

Usually there is a relevant delay between sdram clock source (the pll which also generates system clock) and the sdram pin, whereas system clock has well controlled delays, being wholly inside the fpga.

For optimal performance you should account for this delay, normally applying a phase lead to sdram clock.

For example, on my board I have both clocks at 100MHz, with sdram clock leading sys clk by 27 degrees.

Results from timing analyzer help you to find out the optimal phase shift, depending from fclk and setup/hold requirements of your devices.