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DR123's avatar
DR123
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6 years ago

PLL reset input with Dynamic Phase Shifting

Hi, I'm able to dinamically change the phase of an output clock of a PLL, but I have timinig issues on the input reset of the PLL. In particular, Quartus highlights a relation with negative setup sl...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello, I am not sure about the timing issue you talking about, but about the reset can you use the PLL lock as the reset signal for the internal logic ?

Note : as along as input clock is stable Lock output will be stable .

Can i know why you looking for the reset signal ? i mean any specific reason ?

Thank you ,

Regards,

Sree