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Altera_Forum
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14 years ago

PLL Relock problem

Hi, i used a pll in EP3C40F484, the pll had two clock input pins and a switch input pin. in my logic, i used switch input to select the input clock (inclk0 or inclk1), however, when i changed ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Do You use PLL core clock switch option or You just have a mux, which select a clock before PLL input?