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Altera_Forum
Honored Contributor
Honored ContributorPLL reconfiguration problem
Hi, i want to reconfigure a pll by sending my data chain.When i create my pll with 40 MHz with megawizard it works perfectly.I can set various frequencies. But when i create my pll with 65 MHz ...
Altera_ForumHonored Contributor
Honored ContributorIs your pll controlling any signal that goes out of the FPGA, on the same bank than your 50MHz input? If yes, too many simultaneous switching signals on a bank output could introduce noise that makes the pll loose its lock, especially if the bank's IO supply isn't decoupled enough.
