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Altera_Forum's avatar
Altera_Forum
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12 years ago

PLL reconfiguration problem

Hi, i want to reconfigure a pll by sending my data chain.When i create my pll with 40 MHz with megawizard it works perfectly.I can set various frequencies. But when i create my pll with 65 MHz ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Sacko,

in order to better understand your problem I would like to ask you, which FPGA chip and which Development board are you using?

The ALTPLL can normally manage the internal PLLs and generate the frequency you want according to the FPGA you have available. I would like to ask you also which reference frequency are you using to feed the ALTPLL block and which error does it present to you in case you get one by the compilation process.

BR,

Giovanni