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Honored Contributor
Honored ContributorPLL question about Cyclone III EP3C16
Hi, all, Currently I am designing a board with Cyclone III FPGA EP3C16. And I want to use the PLL function. When I check the Pin function, there are always two pins for PLL Clock out. One is P...
Altera_ForumHonored Contributor
Honored Contributorhttp://www.altera.com/literature/dp/cyclone3/ep3c16.pdf
Looks like you can use PLL_CLKOUTp as a single-ended output. Not sure if you can use PLL_CLKOUTn as a user I/O if using PLL_CLKOUTp as a PLL clock output. A simple test build would answer that question. Another handy document is: http://www.altera.com/literature/dp/cyclone3/pcg-01003.pdf
