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Altera_Forum
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17 years ago

PLL problem after power on reset

Hi, I'm sending data from an arriagx using the lvds block to a stratix fpga, looped through the stratix and back out to the arriagx. There are four lvds blocks involved and each has it's own pl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

We're using 8b/10b with xaui. I read in a document that on power-up you want to supply x number of clocks with a pattern so that it aligns - I think it was 256 or something like that. Apart from that, does the dpa need to be reset if it falls out of lock?

Thanks