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Altera_Forum's avatar
Altera_Forum
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17 years ago

PLL problem after power on reset

Hi, I'm sending data from an arriagx using the lvds block to a stratix fpga, looped through the stratix and back out to the arriagx. There are four lvds blocks involved and each has it's own pl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I have made some progress in that the PLL's seem to be stable now - I'm still in the process of testing just to make sure it's going to hold.

I do have DPA switched on the LVDS in the Stratix and I don't have it switched on in the Arria. What I noticed was that with the Stratix you can choose the edge but with the Arria it uses both edges. Does this make any difference? With the Stratix, all I've don is enable DPA and that's it really. I know there are other things you can enable but I don't if they are needed to control it.

How does the calbration phase actually work? What's the best way to implement it? Right now, I don't think we would mind the software overhead of setting it up in order to make sure it's all working right.

Thanks