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Altera_Forum's avatar
Altera_Forum
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17 years ago

PLL problem after power on reset

Hi, I'm sending data from an arriagx using the lvds block to a stratix fpga, looped through the stratix and back out to the arriagx. There are four lvds blocks involved and each has it's own pl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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I am sorry but I don't agree with the "guarantee".

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I didn't experience such strange PLL behaviour up to now and also haven't a plausible explanation. But it apparently can happen. In this case, Stratix/Arria dynamic phase allign would be the only way to get a reliable LVDS connection. I prefer it anyway, but of course it implies some software overhead, e. g. to signal a calibration phase.